Realizing Low Power FPGAs: A Design Partitioning Algorithm for Voltage Scaling and A Comparative Evaluation of Voltage Scaling

With an exponential rise in logic density and performance, FPGAs are becoming essential components in various electronic systems. However, increased logic density and more importantly programmability of FPGAs cause increased power dissipation, which limits deployment of FPGAs in power constrained consumer electronic products such as mobile systems. Voltage scaling is a well-known tool to reduce power and recently there is a lot of interest in applying this technique to FPGA architectures to reduce power. While it is important to have new architectures to support voltage scaling, it is equally important to have a new CAD tools to create voltage scaling ready designs for different architectures. Our first contribution in this paper is a power driven partitioning algorithm, which creates voltage scaling ready partitions. The design partitions can then be placed onto different voltage island topologies for a single FPGA or onto different FPGAs for a multi-FPGA system having different supply voltages. Due to the discrete routing architecture of FPGA any constraint in the placement stage leads to higher penalty in terms of channel width and critical path delay. Our second contribution is to present different voltage island topologies and a detailed evaluation of each fabric in terms of overheads due to constrained placement of partitions namely critical path delay, channel width and area delay product. We show that as high as 47% dynamic power gain is possible with 17% area delay product penalty and 30% power gain is possible with as low as 6% area delay product penalty for different voltage island configurations in FPGAs.